Understanding Processor Microarchitecture
Extra materials for the combined MIPSfpga and Connected MCU seminar by Imagination Technologies
October-November 2016

Quiz

Name ___________________________________________________________________

1. What is the formula for program execution time?

a) Execution Time = (#instructions)(cycles/instruction)(cycle/seconds)
b) Execution Time = (#instructions)/(cycles/instruction)(seconds/cycle)
c) Execution Time = (#instructions)(cycles/instruction)(seconds/cycle)
d) Execution Time = (#instructions)(instruction/cycles)(seconds/cycle)
e) Execution Time = (#instructions)/((cycles/instruction)(seconds/cycle))

2. What is the major limitation for in-order single pipeline
microarchitectures with deep (long) pipelines?

a) Lack of parallelism in multiple instruction processing
b) Frequent pipeline flushes during jumps
c) Instruction dependencies
d) For special applications, like graphics, requires special programming
e) Memory sharing between processors

3. What kind of cache is likely to be shown on the picture (marked by "?")?

a) Direct L1 cache

b) Two-way L1 cache

c) L2 cache



Sources of pictures:

See MIPS Run Linux (2nd Edition, 2006) by Dominic Sweetman
http://imgtec.com

Quiz is created by Yuri Panchul